I've posted a new Application Note -- AN8 -- that has a more detailed description of the Memory Subsystem. See AN8 The Memory Subsystem and Memory Addresses.txt.
I've posted a new Register Array slide. See Register Array.
I've posted a new Comparators slide deck. See Comparators.
Problem Set 4 has been revised to include additional requirements and details in problems 6 through 8, inclusive.
The due date for the VHDL Counter in Problem Set 3 is now one week later. It is now due on March 15, 2020.
Problem Set 4 has been revised to include extra credit sections.
Please perform pin assignments for VHDL in PS3 and for all VHDL code in this class using the attribute chip_pin method discussed in the VHDL slides.
After the upcoming Spring 2020 semester, the next time CSCI E-93 will be offered is in the Fall 2021 semester.
We will be holding our first section meeting on Tuesday, January 28, 2020 at 6:45 PM ET. Note that this section meeting is *before* our first class meeting. Both section and class meetings are live streamed and are also available after class for later viewing and reviewing.
Many links in the course website are not yet available. They will be activated as the course progresses.
Final Project Presentation Slots:
7:00 PM - 7:15 PM
Filled by Harry
7:15 PM - 7:30 PM
Filled by Mark
7:30 PM - 7:45 PM
Filled by Al
7:45 PM - 8:00 PM
Filled by Bob
8:00 PM - 8:15 PM
Filled by Sandeep
8:15 PM - 8:30 PM
Filled by Nanako
8:30 PM - 8:45 PM
Filled by Eric
8:45 PM - 9:00 PM
Filled by Alan
9:00 PM - 9:15 PM
Filled by Kevin
9:15 PM - 9:30 PM
Filled by McCoy
9:30 PM - 9:45 PM
Filled by Richard
9:45 PM - 10:00 PM
Filled by Martin
Tuesdays 8:00-10:15 PM ET in 53 Church Street, Room L01.
Distance Learning Links including Video Streaming, Chat, and the Midterm Exam:
In addition to being able to participate in section & class in person, both are live streamed and also recorded. Students are encouraged to share their video feed and to ask questions verbally using their audio/video link in HELIX Classroom/Zoom. The section & class live video stream is available through the class Canvas web site under Class Meetings.
Questions can also be asked using the text Chat facility in HELIX Classroom/Zoom during class meetings & during section meetings. Please use the chat feature available in HELIX Classroom/Zoom rather than Canvas chat. We will *not* be monitoring Canvas chat.
Videos of class and section are available on the course's Canvas web site under Class Meetings.
Our midterm exam is a three hour long proctored exam. Students unable to come to campus for the midtem exam can make arrangements to take the exam in absentia in a proctored setting, at an alternative location. Of course, any student -- including distance students -- may choose to come to campus to take the exam. Students who do not take the exam on campus in our classroom are required to procure the services of a Harvard-approved proctor as described in https://www.extension.harvard.edu/resources-policies/exams-grades-transcripts/exams-online-courses. That document states that the exam must be taken "within a specific 24-hour period." In our case, the 24-hour period starts on the date and time of our in-class exam and ends 24 hours later. That is, the exam must be started within that 24-hour period.
The exam allows open-book access to *only* the three required textbooks. No notes are allowed. No electronic devices are allowed.
Knowledge of data structures and programming experience CSCI E-22 (formerly CSCI E-119) (Data Structures) with some background in boolean/digital logic preferred, but not required ENSC E-123 (Laboratory Electronics: Digital Circuit Design) or equivalents.
A study of the fundamental concepts in the design and organization of modern computer systems. Topics include computer organization, instruction set design, processor design, memory system design, timing issues, interrupts, microcoding, and various performance-enhancing parallel techniques such as prefetching, pipelining, branch prediction, superscalar execution, and massive-parallel processing. Study of existing architectures using CISC, RISC, vector, data parallel, and VLIW designs. An extensive lab project will be required of all students.
4 credits. Graduate credit.
Computer Science E-93 is a comprehensive course in the architecture and organization of modern computers. Students are already expected to be comfortable with designing, coding, and debugging programs of modest complexity while employing good programming style, structured techniques, and employing appropriate data structures as appropriate. In particular, this class is not a programming course, but students will be required to write several significant programs. In addition, some experience with digital logic and gates and with programming in assembler language is preferred.
A significant portion of the class will involve the design and implementation of a major term project. The project will be developed by each student working alone. That project is the core of a new computer's central processing unit including the data path, instruction fetch and decoding unit, and registers implemented using an Altera FPGA. Initially, both the classroom lectures and the section meetings will be covering material important to the design and implementation of the final project. Later in the semester, advanced topics will be covered in class; however, both the class and sections will continue to support students as term projects progress. Throughout the semester, students will be working on and debugging their projects leading to their complete implementation and demonstration.
Because the course requires a significant term project involving both programming and hardware implementation, the assignments will be time-consuming; therefore, a significant time commitment to the course is necessary. Although the relevant experience of students in the class is usually quite diverse, depending on background, it is not unusual for students to spend 15-20 hours per week or more completing the readings and homework assignments. Although the computers are available more-or-less around the clock, occasionally they will suddenly become unavailable (this is known as a crash). As with all such events, they always seem to occur at the worst possible time. Plan your computer work so that it is complete in advance of the deadlines. You have now been forewarned!
All course books are available from the Harvard Coop and are on reserve at Lamont Library. There are links available on Canvas to find the Libary Reserves and, for some books, these include View online versions. A direct link to the books at the Coop is available for on-line purchasing. In addition, all registered students will be eligible for library services (access, borrowing privileges, group study rooms) in FAS libraries, just like any other student in FAS. All registered students will continue to have access to Harvard Library online resources.
Contemporary Logic Design, Second Edition; Randy H. Katz and Gaetano Borriello; Prentice Hall Inc., 2005; ISBN-13 978-0-201-30857-0; ISBN-10 0-201-30857-6; Errata for the Second Edition
Computer Organization and Design: The Hardware/Software Interface, Fifth Edition; David A. Patterson and John L. Hennessy; Morgan Kaufmann/Elsevier, September 2013; ISBN-13 978-0-12-407726-3; Errata for the Fourth Revised Edition; Errata for the Fifth Edition
The Designer's Guide to VHDL, Third Edition; Peter J. Ashenden; Morgan Kaufmann/Elsevier, May 2008; ISBN-13 978-0-12-088785-9; ISBN-10 0-12-088785-1; Errata for the First to Fourth Printings
Optional Additional Digital Electronics Book:
Digital Systems: Principles and Applications, Twelfth Edition; Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss; Prentice Hall Inc., 2017; ISBN-13 978-0-13-422013-0
Optional Electronics Books:
The Art of Electronics, Third Edition; Paul Horowitz and Winfield Hill; Cambridge University Press, April 2015; ISBN-13 978-0521809269
Learning the Art of Electronics: A Hands-On Lab Course; Thomas C. Hayes and Paul Horowitz; Cambridge University Press, March 2016; ISBN-13 978-0521177238
Optional Additional Computer Architecture Books:
Computer Architecture: A Quantitative Approach, Sixth Edition; John L. Hennessy and David A. Patterson; Morgan Kaufmann/Elsevier, November 2017; ISBN 978-0-12-811905-1
MIPS RISC Architecture, Second Edition; Gerry Kane and Joseph Heinrich; Prentice Hall Inc., 1992; ISBN-13 978-0-13-590472-5; ISBN-10 0-13-590472-2
Modern Operating Systems, Fourth Edition; Andrew S. Tanenbaum and Herbert Bos; Prentice Hall Inc., 2015; ISBN-13 978-0-13-359162-0; ISBN-10 0-13-359162-X
Optional VHDL Book:
Fundamentals of Digital Logic with VHDL Design with CD-ROM, 3rd Edition; Stephen D. Brown and Zvonko G. Vranesic; McGraw-Hill Higher Education, 2009; ISBN-13 978-0-07-722143-0; ISBN-10 0-07-722143-5. As of 2019, this book is out of print. This book includes a CD-ROM with the student edition of Altera's MAX+PLUS II CAD software. There is also a website for this book.
Optional git Books:
Dangit, Git!: Recipes for Gitting out of a Git Mess; Katie Sylor-Miller and Julia Evans; This short on-line book describes git fundamentals.
Pro Git, 2nd Edition; Scott Chacon and Ben Straub; Apress, 2014; ISBN-13 978-1484200773; ISBN-10 9781484200773. This is a comprehensive book about git. It is also available for free download at the web site above.
There will also be other handouts & supplementary readings
Instructor:Dr. James L. Frankel ,
We have two Teaching Assistants (TAs) for the course. The TAs hold a weekly section and office hours as described below. Attendance at the section is strongly recommended. When appropriate to send e-mail, please send e-mail to both TAs and to the course instructor.
|TA||Section Meeting Time/Place||Office Hours Time/Place||E-mail Address/Phone|
6:45-7:45 PM ET,
1 Story Street, Room 303
6:30-7:30 PM ET by appt. only,
Science Center, Room 101e
|E-mail: ; +1.978.496.7213 (1:00 PM - 9:00 PM ET). If there's no answer, please leave a message with your name and a call-back number. Questions whose answers would be relevant to the whole class should be posed via Piazza. When e-mail is appropriate (for grading questions, personal issues, etc.), e-mail should be sent to both TAs and also to the professor.|
6:45-7:45 PM ET,
1 Story Street, Room 303
6:30-7:30 PM ET by appt. only,
Science Center, Room 101e
|E-mail: ; +1.303.803.2261 (11:00 AM - 9:00 PM ET). If there's no answer, please leave a message with your name and a call-back number. Questions whose answers would be relevant to the whole class should be posed via Piazza. When e-mail is appropriate (for grading questions, personal issues, etc.), e-mail should be sent to both TAs and also to the professor.|
We'd all like to meet the other students in the class -- both near and far. Please use the Canvas Say Hello! facility to upload a brief video (about a minute or two in duration) introducing yourself to the class.
Also, please post your primary location using the Canvas Student Locations facility.
Undergraduate-credit and graduate-credit students:
All problem sets and programming assignments are due at midnight Eastern Time on Sunday night (i.e., midnight between Sunday and Monday) unless otherwise stated in the assignment or in the syllabus. Unless otherwise stated, all programming assignment solutions must be written in C, C++, or Java, have run successfully on our Amazon EC2 Linux AMI instance with hostname is cscie93.dce.harvard.edu or on the Altera DE2-70 or DE2-115 FPGA system, as appropriate, be submitted using "git" on https://github.com/ (or, in dire circumstances, via e-mail only if agreed to by your TA), be well-written (clear coding style, modular structure, appropriately commented and documented in English), and tested (include any programs and/or shell scripts used in testing your solution as part of your submission). Of course, the solutions may be written and tested using any system of the student's choosing; however, when the solution is complete, it must be pushed to the git code repository on https://github.com/. If you don't have your own native Unix/Linux system and run under Windows, you may find it useful to use code development tools under Cygwin. We will be grading the Unix/Linux solutions based on their behavior on the cscie93.dce.harvard.edu computer. Therefore, you should make sure that the final version of Unix/Linux programs that you submit for grading works properly on the cscie93.dce.harvard.edu computer. In addition, each submission must include a makefile to build the assignment. The grade for programming assignments will include all of these attributes.
You can establish an account on cscie93.dce.harvard.edu by accessing the website at URL https://ac-web.dce.harvard.edu/ and clicking on "Reset Password." Please note that the username shown on this screen is the username you will use to login to our server. Our cscie93.dce.harvard.edu computer may be accessed for remote login using "ssh" over the Internet. Files may be transferred to these systems using "secure ftp" (SFTP). If you are using a Windows system, the SecureCRT and SecureFX programs are available from the Science Center at http://downloads.fas.harvard.edu/download; these programs implement "ssh" and "secure ftp," respectively. On Unix/Linux systems, the shell commands "ssh" and "sftp"/"scp" can be used for ssh and SFTP, respectively. Remember, in addition to handing in all parts of the problem set solution or programming assignment program, sample runs of the program which demonstrate that the program works must be attached.
Some assignments may include Extra Credit programming problems. The Extra Credit programming problems can be completed to earn points that can increase the overall grade on the programming portion of your problem set; however, the grade on the programming portion of a problem set including extra credit will ever exceed the full credit possible grade on the programming portion. That is, the Extra Credit programming problem(s) can be used to make up for deficiencies in other programming portions of the problem set to allow a higher grade to be earned. Extra Credit points from one problem set are not transferrable and may not be used on any other problem sets.
All problem sets except for Problem Set 0 may be submitted late for partial credit. A late homework will lose 5% of its original grade for each day it is late (e.g. an assignment handed in two and a half days late will receive its original grade multiplied by 0.85). Late assignments may be submitted via GitHub and an e-mail message notifying the instructor and the teaching assistants should be sent immediately after the late assignment is submitted. In addition, each student is given five free late days that may be used freely during the semester. However, keep in mind that almost all of the assignments are built on the previous assignments; handing in one assignment late does not extend the due date for subsequent assignments. The scope and difficultly level of the assignments increases during the class; therefore, we recommend against using the five free late days early in the class.
Problem sets may also be revised and/or completed and resubmitted late for partial credit devalued by the same 5% rule detailed above for each day late it is resubmitted.
Commented and Documented:
In the "Grading: Problem Sets" section above, the phrase "commented and documented" is used; this paragraph will clarify the necessary comments and documentation that should be provided with all programs. First, there should be a description of the entire application. This should include the user interface (i.e., how a user interacts with the program) and an explanation of what the program does. This documentation may be in a separate file from the program itself. Second, there should be a description at the beginning of each file which outlines the contents of that file. Third, each routine, function, method, etc. must be preceded by a section describing: (1) the name of the routine, (2) the purpose/function of the routine, (3) the parameters to the routine (name, type, meaning), (4) the return value from the routine (type, meaning), and (5) any side-effects (including modifying global variables, performing I/O, modifying heap-based storage, etc.) that the routine may cause. Fourth, declarations of variables should be commented with their purpose. Fifth, blocks of code should be commented to describe the purpose of the code section. Sixth, any complex or difficult to understand code statements or fragments should be commented to clarify their behavior.
In addition to programming in conventional languages (either C, C++, or Java), students will learn how to write code in VHDL. This is the Hardware Description Language that we will use to configure the Altera FPGA. All students are required to use the Altera Quartus II Web Edition Software, Version 13.0, Service Pack 1, released June, 2013. This software may be downloaded from the Altera web site, is free, and no license is required. The software runs only on either Windows or Linux. The specific version of Altera Quartus software that students should use may be updated during the class term.
When using "git" and https://github.com/, make sure to follow the information on using "git" and setting up your repository that is available on the section web site. Create a named branch for each of your problem sets as follows: specify "problem-set-0" for Problem Set 0 (the course questionnaire, fix this program, and word count), specify "problem-set-1" for Problem Set 1, "problem-set-2" for Problem Set 2, etc., specify "prelim-term-project" for the Preliminary Final Project Problem Set, and specify "term-project" for the Term Project.
See Distance Learning Links: Midterm Exam for more information for distance students.
All work should be the personal creation of the individual student. Students are free to consult with each other and to study together, but all problem set solutions, programming assignments, exams, and the final project must be the personal contribution of each individual student. More explicitly, whenever a concept is reduced to a detailed algorithm or a program, no collaboration is allowed. If a paper, assignment, exam, program, or final project contains any information, algorithms, program fragments or other intellectual property taken from another source, that source and material must be explicitly identified and credit given. If you have any questions about this policy, it is the student's responsibility to clarify whether their activity is considered plagiarism.
|7||Registration opens at 9 AM ET for degree candidates.|
|12||Registration opens at 9 AM ET for all students.|
|20||Martin Luther King Jr. Day|
|23||Registration deadline. Last day to register for spring term courses. Late registration is not permitted after this date.|
|24-February 2||Course change period For registered students only|
|28||Introduction, course information & policies, outline, schedule. Review of simple digital logic.|
|2 at Midnight||Problem Set 0 (using git, the course questionnaire, fix this program, and word count) due.|
|2||Course changes deadline. Course drop deadline for full-tuition refund.|
|4||Flip-flops as memory building blocks. Advanced Boolean
logic, computer arithmetic, useful laws and theorems, sum of
products form, minimization, technology metrics.
For today, read Katz chapters 1 and 2 and Patterson/Hennessy appendix B (4/e revised printing: appendix C) on The Basics of Logic Design.
|9||Course drop deadline for half-tuition refund|
|9 at Midnight||Problem Set 1 due.|
|11||Place values, numeric encodings, gray codes & Karnaugh
maps, canonical forms (minterms & maxterms), dealing with time
in combinational logic networks, MIPS assembly language
programming and instruction set design, addressing modes.
For today, read Katz chapter 3 and Patterson/Hennessy chapters 1 and 2 (4/e revised printing: chapters 1 and 2) on Computer Abstractions and Technology, and Instructions: Language of the Computer.
|18||Designing a processor: the datapath and control logic,
Continue to discuss the MIPS instruction set and a simple
block diagram of its implementation.
Distribute Altera/Terasic hardware.
For today, read Katz chapter 4 and Patterson/Hennessy chapter 4 (4/e revised printing: chapter 4) on The Processor.
|23 at Midnight||Problem Set 2 due.|
|25||Discuss the instruction sets for the PDP-8 and the PDP-11.
For today, read Katz chapters 5 and 6 and Patterson/Hennessy chapter 3 (4/e revised printing: chapter 3) on Arithmetic for Computers.
|3||Waveform diagrams, glitches, and hazards. Complete the
PDP-11 instruction set including subroutines and condition
codes. Endianness. Finite state machines. Material to be
covered in the midterm exam.
For today, read Katz chapters 7 and 8.
|8 at Midnight||Problem Set 3 due.|
For today, read Patterson/Hennessy chapter 5.6-5.18 (4/e revised printing: chapter 5.4-5.14) on the memory hierarchy.
|24||Details of implementing an assembler. MIF file
description. Performing I/O operations using memory-mapped
I/O. The interface to our memory subsystem.
For today, read Patterson/Hennessy appendix A (4/e revised printing: appendix B) on Assemblers, Linkers, and the SPIM Simulator and Patterson/Hennessy chapter 5.2, 5.11 (4/e revised printing: chapter 6) on I/O devices.
|29 at Midnight||Problem Set 4 due.|
|31||Review the midterm exam. Serial communication, Caching,
For today, read Patterson/Hennessy chapter 5.1-5.5 (4/e revised printing: chapter 5.1-5.3) on caches.
|5 at Midnight||Preliminary Final Project Problem Set due.|
|7||Virtual memory (continued), TLB's (Translation Lookaside Buffers), Page Replacement strategies, Basic electronics, Pipelining.|
|12 at Midnight||Problem Set 5 due.|
Pipelining (continued). Parallelism. SISD, SIMD, & MIMD
architectures. Locality of data to processor.
For today, read Patterson/Hennessy chapter 6 (4/e revised printing: chapter 7) on parallel processing.
|21||VLSI circuit (custom silicon) design.|
|24||Withdrawal deadline (no tuition refund)|
|26 at Midnight||Problem Set 6 due.|
|28||I/O (Input/Output) Systems, interrupts. Vector computers. Data parallel computers.|
|5||RISC vs. CISC architectures. VLIW (Very Long Instruction Word) computers. Mapping a high-level language onto a low-level architecture. Additional topics.|
|11-16||Final exams and last class meetings|
|12||Final Class Meeting during usual section and class time. Student project presentations/demonstrations. Term Project due.|
|15 by 2 PM ET||All Final Project code, documentation, and presentation material must be submitted.|
|15 between 5 PM ET to 7 PM ET||Alternate and final time to return all borrowed hardware.|
|26||Grades available online in Online Services|
Hardware Related References:
The class project will use the Altera Cyclone II FPGA (EP2C70F896C6N) on our Altera Development and Education DE2-70 boards (or alternatively, the Altera Cyclone IV FPGA (EP4CE115F29C7) on DE2-115 boards). Students taking the course in person in Cambridge will be able to borrow the hardware for use during the semester. Distance students must purchase their own Altera DE2-115 Development and Education Board. This hardware is available at academic pricing from the Terasic web site.
As mentioned above, the Quartus II software that we will be utilizing to program the FPGAs, runs only on either Windows or Linux. We strongly recommended that only the Windows version be used. For those of you using Apple Mac computers and macOS, running Quartus II under a VM on a Mac works well.
Altera information is available for:
As stated on the Altera web site, Quartus II version 13.0sp1 supports all Altera University Program FPGA boards, including our DE2-70 and DE2-115 boards. This is the version of Quartus II that we will all be using in the class. Although new versions of the Quartus II software will be developed and released each year by Altera, Quartus II version 13.0sp1 will continue to be maintained and updated for the foreseeable future.
The Quartus II software starting from version 13.1 does not include support for the Cyclone II family of FPGAs, which are used in DE2-70 boards. Note that the DE2-115 board uses the Cyclone IV family, and so is not affected. The Cyclone IV family of FPGAs is still supported in Quartus II version 17.0.
In addition, starting in Quartus II version 14.0 there will no longer be support for 32-bit computers (Quartus II V14.0 can only be used on 64 bit computers).
Older class projects used the Altera FLEX 10K device (EPF10K70RC240-4) on Altera University Program UP2 boards. Support for the Altera FLEX 10K device family has been removed from Quartus II software version 9.1 and future releases. The last support for these device families is version 9.0 SP2, which will be available permanently on Altera's Download Center.
When we were using the UP2 Education Board, the programming cable that we used was the USB Blaster Cable manufactured by Terasic, but it is identical to the Altera USB-Blaster and uses the same drivers.
Altera information is available for:
Sample Altera VHDL documents are:
CSCI E-93 Application Notes for using the Altera FPGAs:
Laboratory Documents and Programs:
USB to Serial Adapter:
Static dissipative devices used in the lab:
The ring terminal at the end of the common point ground wire should be attached to the nearest electrical outlet faceplace using the screw between the outlets of a duplex outlet. Note that the alligator clips connected to the wires on both the anti-static mat and the wrist strap are removeable. The alligator clips are actually adapters from banana plugs to alligator clips similar to . After the alligator clip adapter is pulled off, the banana plug can be plugged into one of the two banana jacks on the common point ground.
Software and Course Documents On-Line:
Slides used in class
The Course Questionnaire and Problem Sets
Online Software: Windows 10, GNU, Cygwin, Windows Subsystem for Linux, Google Drawings, Visio, Dia, OmniGraffle, draw.io, SPIM, etc.
Electronics stores in the Greater Boston Area
Electronics distributors on the Web
Hardware distibutors on the Web
Harvard University Information Technology
Section Home Page