Description of the processor-memory interface


The processor and memory are connected by the following lines:

* mem_addr(20 downto 0):       Address lines (21); these lines are
			       driven by the processor
* mem_data_read(31 downto 0):  Input data lines (16+8+8); these lines
			       are driven by the memory
* mem_data_write(31 downto 0): Output data lines (16+8+8); these lines
			       are driven by the processor
* Control lines:
*** mem_rw: The processor controls this line to specify the memory
    operation (i.e., read vs. write).
	0 = read memory, 
	1 = write memory
*** mem_sixteenbit: The processor controls this line in conjunction
    with the mem_thirtytwobit control line to specify the data width
    for the operation.  For either 8-bit or 16-bit memory access
    modes, the mem_thirtytwobit control line must be zero (i.e., the
    mem_thirtytwobit control line has higher precedence).  Note that
    in byte memory access mode, only the lower 8 data bits are
    relevant.  In word memory access mode, the lower 8 data bits are
    read/written from/to the specified address and the higher 8 data
    bits are read/written from/to the specified address plus one.  In
    word memory access mode, the specified address must be word
    aligned (i.e., the least significant bit of the address must be
    zero).
	0 = byte memory access (8 bit)
	1 = word memory access (16 bit)
*** mem_thirtytwobit: The processor controls this line in conjunction
    with the mem_sixteenbit control line to specify the data width for
    the operation.  For either 8-bit or 16-bit memory access modes,
    the mem_thirtytwobit control line must be zero (i.e., the
    mem_thirtytwobit control line has higher precedence).  In double
    word memory access mode, the lower 8 data bits are read/written
    from/to the specified address, the next higher 8 data bits are
    read/written from/to the specified address plus one, and so on
    with the most significant 8 data bits read/written from/to the
    specified address plus three.
	0 = either byte or word memory access (8 bit or 16 bit) as
	    determined by mem_sixteenbit
	1 = double word memory access (32 bit)
*** mem_addressready: The processor controls this line used in the
    handshake as described below.
*** mem_dataready_inv: The memory controls this line used in the
    handshake as described below.
*** mem_reset: The processor controls this line to reset the memory
    controller to its initial state.  An active-high signal on this
    line causes the memory controller to be reset to its initial state.
*** mem_suspend: The processor controls this line to cause the memory
    subsystem to stop responding to any memory requests.  Even when
    mem_suspend is asserted, the generated clocks will continue running.
    An active-high signal on this line causes the memory subsystem to
    stop responding to any memory requests.


The memory handshake protocol (as seen from the processor side) is:

1) Wait for mem_dataready_inv to go high.
2) Set the address lines (mem_addr), mem_rw line, mem_sixteenbit line,
   and mem_thirtytwobit line.
3) Set mem_addressready high.
4) Wait for mem_dataready_inv to go low.
5) mem_addr, mem_rw, mem_sixteenbit, and mem_thirtytwobit no longer
   need to be kept stable.
6) If the operation is a read (i.e., mem_rw is low), read the input
   data from the input data lines (mem_data_read).
7) If the operation is a write (i.e., mem_rw is high), then set the
   output data lines (mem_data_write) with the appropriate data to be
   written to memory.  Of course, the mem_data_write lines can be set
   earlier (for example, in step 2 when the other lines are set).
8) Set mem_addressready low.
9) Wait for mem_dataready_inv to go high if you want to know that the
   write to memory has completed.
10) mem_data_write no longer needs to be kept stable.
The next cycle starts with: 1) Wait for mem_dataready_inv to go high.


The corresponding cycle in memory is:

The cycle starts when the memory sets mem_dataready_inv high.
1) Wait for mem_addressready to go high.
2) Read mem_addr, mem_rw, mem_sixteenbit, mem_thirtytwobit lines and
   latch these values.
3) If a read operation is requested (i.e., mem_rw is low), fetch the
   appropriate data and set the input data lines (mem_data_read) to
   represent that data.
3) Set mem_dataready_inv low.
4) Wait for mem_addressready to go low.
5) mem_data_read no longer needs to be kept stable.
6) If a write operation is requested (i.e., mem_rw was high when read
   in step 2), then read the output data lines (mem_data_write) and
   store that data into memory at the address read in step 2.
7) Set mem_dataready_inv high.