Problem Set 6

		 Harvard Extension School CSCI E-93:
			Computer Architecture

			      Fall 2024

	 Due: November 24, 2024 at Midnight ET (Eastern Time)

Total of 100 (problem set) + 10 (10% of final project grade) Points

Please submit your solution to this problem set using "git" with named
branch problem-set-6.

For this assignment, based on your architecture design from Problem
Set 2 with appropriate modifications made by you based on comments and
design changes, and with your solution to Problem Set 5 (the emulator
for your architecture design), complete the following assignment.

1. (100 Points counted toward the grade for problem sets) Produce a
   detailed description of the actions taken by your processor on each
   processor cycle and for each edge of each clock phase.  Your
   description should include the conditions under which the action is
   taken -- for example, only when a particular instruction is present
   in the IR (Instruction Register) or only when the condition code
   produced by the ALU (Arithmetic Logic Unit) indicates a zero
   result.  This complete description is tantamount to a description
   of the microcode for your processor should your design be
   microcoded.

   The solution to this problem should begin with a description of
   your overall clocking scheme (i.e., what happens on each clock edge
   and while the clock is either low or high).  The remainder of the
   solution to this problem should be a spreadsheet/table with the
   following columns:

     (1) A name for this action (such as, Reset, ReadMemInstr,
     InstrALUOp, InstrBranch, InstrJump, InstrLoad, etc.)  -- this
     name will likely be the same name that will be used as the state
     in your VHDL FSM for your processor's sequencer,

     (2) A textual description of what is happening in this action,

     (3) The specific CPU control lines that are asserted to
     accomplish the action,

     (4) The possible next states after this state (such as, Goto
     ReadMemInstr3 unconditionally, Goto ReadMemData if
     mem_dataready_inv == 0b0, Goto InstrBranchTrue if (IR[15-12] ==
     0b0110) && (ALUResultZero == 0b1)) along with a textual
     description of what the condition means (e.g., Progress to the
     next state (#3) in the memory handshake protocol, The memory
     subsystem has completed the read so we progress to the next state
     (#5) in the memory handshake protocol, Our branch condition is
     true).

2. (10 Points counted toward the grade for the final project not
   toward the grade for problem sets) Write VHDL code to interact with
   the memory subsystem to read and write a 16-bit word.  Your VHDL
   code should be an implementation of a finite state machine or FSM
   (or, if you prefer, an FSM invoked from another FSM) executing in
   the Altera DE2-115 FPGA.  It should read a word from location
   0x1dea and then write the value that was read into location 0x0b0e.
   Both the read and the write should be issued in 16-bit mode.  After
   completing the write, the FSM should begin the same process again
   without termination.  This code will serve as your memory interface
   in the final project.

   Use pushbutton KEY3 on the DE2-115 board to serve as the mem_reset
   line to the memory subsystem.

   Use slide switch SW17 on the DE2-115 board to serve as the
   mem_suspend line to the memory subsystem.

   Your VHDL code should use the clocks generated by the memory
   subsystem -- they are named sysclk1 and sysclk2 -- as the clocks
   for all logic on the DE2-115 board.

   Use slide switch SW16 on the DE2-115 board to serve as the
   clock_hold line to the memory subsystem.

   Use pushbutton KEY2 on the DE2-115 board to serve as the clock_step
   line to the memory subsystem.

Please include with this assignment an up-to-date copy of your
processor's block diagram and an up-to-date copy of your processor's
instruction set.


			Last revised 1-Sep-24