Final Project

		 Harvard Extension School CSCI E-93:
			Computer Architecture

			      Fall 2024

		      Due: December 17-20, 2024

For the final project, based on your architecture design from Problem
Set 2 with appropriate modifications made by you based on comments and
design changes, and using the VHDL code for your ALU, complete the
following assignment.

Please submit your solution to this problem set using "git" with named
branch term-project.


Produce VHDL code for your entire processor design.  This includes the
data path, the ALU, the memory interface, and the sequencing logic.
The final design should be implemented using the Altera DE2-115 system
in conjunction with the furnished memory subsystem.

The culmination of your final project is to run the assembly language
code that you wrote for your processor in Problem Set 4, Parts 2
through 9 under your processor on the FPGA.  You are welcome to write,
run, and demonstrate additional interesting programs running on your
hardware.

We *will* be holding an elongated class during Final Exam Period (on
Tuesday night, December 17th) that will begin at 6:45 PM ET and will
encompass the time of both section and class.  This entire class
meeting will begin at 6:45 PM ET and will be held in Zoom lecture room
where class lectures are normally held.  During that final class
meeting on December 17th, each class member will be responsible for
presenting their design and demonstrating their project.

Each student will be given a maximum twenty minute slot for their
presentation and Q&A session.  To keep our final presentations on
track, you will create a fifteen minute (timing will be enforced)
*pre-recorded* audio and video presentation of your processor which
will be followed by an additional five minute question and answer
session.  We will be enforcing the fifteen minute time constraint.
Your video presentation is a required part of your participation and
grade in the course.  Your video presentation must be available over
the Internet.  In advance of the class meeting -- by 4 PM ET on
Tuesday, December 17, 2024, all students should send to the course
staff the URL for their fifteen minute pre-recorded presentation.
Included in your presentation should be slides that show your block
diagram, clocking scheme, sequencing logic, interesting design aspects
of your logic, your instruction set, assembler, emulator, special
feature(s), and finally a demo of your project running with the memory
subsystem.  Show a small number of programs running on your hardware
that demonstrate the capabilities of your hardware (including any
novel features you have implemented).

All students may participate in the question and answer session via
Zoom.  We may have a number of guests joining us for the final class
meeting.

By 2 PM ET on Friday, December 20th, each class member should submit
(with git tag term-project) a Final Project report which will include
the slides used during your presentation, an overview of the
processor, an up-to-date copy of the processor block diagram, an
up-to-date copy of your processor's instruction set (i.e., your
Principles of Operation manual), VHDL code for the complete design, a
current copy of the source code for your assembler, a current copy of
the source code for your emulator, and documented sample programs for
your processor.


			Last revised 1-Sep-24